A Functional Compact and Sensitive CMOS Imager Design
Program:
Electrical and Computer Engineering
Project Description:
A CMOS imager design intended for modern mobile applications composed of an array of active pixel sensors (APS). Design is implemented in Cadence using TSMC 0.18u technology node.
Team Members
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Project Mentors, Sponsors, and Partners
Course Faculty
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Additional Project Information
Project Photo
Project Photo Caption:
Overview of a 4×4 APS array for testing purposes