CMOS Imager VLSI Design


Program: Electrical and Computer Engineering

Our team designed a CMOS 3-transistor active pixel imager, detailing circuit schematics and transistor layouts of a camera imager chip. The column- and row-decode module implements cascaded C2MOS shift registers that allows output voltages to be read throughout a 4-by-4 array of pixels sequentially.

The design is created and simulated in Cadence.

Team Members